Example embodiments relate to a data processing system, and more particularly, to a bandwidth synchronization system in mobile systems, for example, smart phones or navigation devices or the like.
In mobile systems such as smart phones, personal navigation devices, portable Internet devices, portable broadcasting devices, and/or multimedia devices, high performance mobile application processors operating at a high frequency are used on a System on Chip (hereinafter, referred to as “SoC”) to support various applications.
Since the mobile application processors perform arithmetic operation, logic operations and/or program command execution, the mobile application processors are elements that are resource intensive (for example, memory intensive) and may affect performance of a mobile SoC. The mobile application processors may include an on-chip secondary cache, referred to as an L2 (level 2) cache, to enable integration of various functions such as wireless communication, personal navigation, camera, portable gaming, portable music/video player, unified mobile TV, and/or Personal Digital Assistant (PDA). The L2 cache may increase the performance of the mobile system during instances of high memory utilization by the processor.
For efficient design of the SoC, selection of a bus system for mutual communication between a plurality of Intellectual Properties (IPs) (for example, memories, controllers, drivers, or the like) integrated on one chip is of high importance. A typical example of a bus system is an AMBA 3.0 Advanced eXtensible Interface (AXI) bus system based on AMBA protocol from Advanced RISC Machine (ARM) Inc.
Because of limitations in, for example, development time and manpower, peripheral functional blocks such as Direct Memory Access Controller (DMAC), Universal Serial Bus (USB), Peripheral Component Interconnection (PCI), Static Memory Controller (SMC), and/or Smart Card Interface (SCI) that are parts of SoC may be purchased as separate IPs. These purchased peripheral functional block IPs may then be integrated on a chip along with a Central Processing Unit (CPU) and other data processing functional blocks to constitute the SoC.
With an increase in demand for high performance mobile application processors, the operating frequency of a CPU and a cache controller in a SoC is in the order of several gigahertz (GHz). On the contrary, because the frequency of the bus may not be increased to a level of several GHz, a data bus width wider than that of the CPU is used to satisfy bandwidth requirements. For example, when the data bus width of a CPU having an operating frequency of about 1 GHz is 64-bit, the operating frequency of the bus system may be designed to have an operating frequency of about 200 MHz and a data bus width of about 128-bit.
A syncdown logic and 64-bit to 128-bit upsizer circuit may be connected to a cache controller and may synchronize about 1 GHz to about 200 MHz between a CPU having a 64-bit data bus width and a 1 GHz operating frequency and a bus system having a 128-bit data bus width and a 200 MHz operating frequency.
In this case, a part of a synchronized syncdown point operating at 64-bit 200 MHz has a bandwidth of about 1.6 GBps, which acts as a bandwidth bottleneck compared to a CPU bandwidth of about 8 GBps or an upsizer bandwidth of about 3.2 GBps. Accordingly, performance of a high frequency CPU as well as a high data width bus system may be reduced.
Therefore, a bandwidth synchronization technology is required to improve the system performance by solving the bandwidth bottleneck in a mobile system.